Data conversion devices of the type utilizing analog-to-digital converters are utilized primarily for the purpose of quantizing analog signals for use in digital signal processing thereof. As the need for more powerful digital signal processing systems increases, the need for higher resolution ADCs increases. However, this increase in resolution also requires the ADCs to provide a much higher level of accuracy.
Most ADCs utilize switched capacitor elements and differential amplifiers. These switched capacitor elements, in order to obtain the necessary accuracy, must be accurately matched. Of course, this then requires the manufacturing process to achieve high levels of accuracy, which are sometimes difficult due to matching limitations between components, which components are fundamentally related to each other in an ADC algorithm by ratios therebetween. Since these limitations usually exceed the process capabilities, various calibration techniques are then implemented.
One type of ADC that has overcome some of the disadvantages noted above is the pipelined analog-to-digital converter. This type of ADC has some advantages over the flash or successive approximation techniques due to potentially high resolution and high speed that can be achieved at the same time. These converters use a plurality of converter stages, each converter stage involving a sub-ADC and a reconstructing digital-to-analog (DAC) converter. In addition, there is a gain element associated with each converter stage in the analog domain. The data conversion techniques utilize a plurality of switched capacitor elements, the output of which is an analog signal that is typically input to a differential interstage amplifier stage to provide the gain element. The implementation of the interstage amplifier utilizing a fully differential amplifier yields superior performance in power supply rejection. However, this is achieved with an interstage amplifier that utilizes common-mode feedback circuitry. This circuitry typically increases area, power and complexity, in addition to introducing parasitics, with a noted decrease in stability and speed.
In the design of accurate pipeline analog-to-digital converters, the gain of each stage is probably the most critical parameter. Other factors aside, the major contributor to gain error is capacitor mismatch. To account for mismatch, techniques have been developed to "trim" capacitors. This, of course, is difficult in that either capacitors must be added or subtracted from a circuit to place them in parallel order or remove them therefrom.